Regviz

Alif Semiconductor /AE512F80F5582LS_CM55_HE_View /DSI /DSI_CLKMGR_CFG

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DSI_CLKMGR_CFG

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Alif Semiconductor/AE512F80F5582LS_CM55_HE_View/DSI/DSI_CLKMGR_CFG#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TX_ESC_CLK_DIVISION 0TO_CLK_DIVISION

Description

Clock Control Register

Fields

TX_ESC_CLK_DIVISION

This field indicates the division factor for the TX Escape clock source (LANEBYTECLK). The values 0 and 1 stop the TXCLKESC generation.
TO_CLK_DIVISION

This field indicates the division factor for the Timeout clock used as the timing unit in the configuration of high-speed to low-power and low-power to high-speed transition error.

Links

()

Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data